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Thursday, September 21, 2017

Intel shows early details of 10nm Falcon Mesa FPGAs

By Nick Flaherty at www.flaherty.co.uk

Intel has released the first details of the FPGAs it plans to make on its 10nm FINFET process. Although the latest processors on the technology have been delayed, FPGAs are a good process prover as they have lots of repeatable elements and lots of redundancy that can survive low process yields.

The Falcon Mesa FPGAs will target data centerr wireless 5G, network function virtualization (NFV), automotive, industrial and military/aerospace applications with 112 Gbps serial transceiver links and the latest PCI Express Gen4 x16 support with data rates up to 16 GT/s per lane for next-generation data centres.

The new family will build upon several innovative technologies from the current Intel Stratix 10 14 nm FPGAs designed by Altera. The Hyperflex architecture, which uses registers, called hyper-registers, throughout the FPGA, is being optimised for 10nm as you would expect, and this will be included in the Quartus Prime high-level design tools.

The Embedded Multi-Die Interconnect Bridge (EMIB) packaging technology will allow the higher performance transceivers to be made on a different process technology and integrated into the package alongside the FPGA fabric. 

A next-generation high bandwidth memory (HBM) DRAM memory architecture will also deliver 10x the performance of discrete memory designs in a smaller form factor with lower power consumption.

More details at a later date, says Intel, and you can see where the technology came from in this story from 2010: Altera heads to 28nm for Stratix V FPGA Family

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