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Thursday, December 07, 2017

Renesas to push onchip flash memory to 100Mbytes

By Nick Flaherty www.flaherty.co.uk

Renesas Electronics has successfully demonstrated a high density embedded flash memory technology for microcontroller built on a 16 or 14nm process (See roadmap above).

The split-gate metal-oxide nitride oxide silicon (SG-MONOS) process technology has been used with fin-shaped 3D transistors as part of the roadmap to large-capacity flash memories of more than 100MBytes.

Renesas is now combining high-performance/low-power logic with large-capacity/high-performance nonvolatile memory implemented with finer feature sizes for future controllers for automotive and the Internet of Things (IoT) .

In 2016, Renesas announced the successful development of the industry's first fin-type SG-MONOS flash memory cell by applying and adopting charge trap type flash memory technology that had been used in the past. The SG-MONOS flash memory performs its data storage in a thin trap film formed on the surface of the silicon substrate, which makes it comparatively easier to deploy it in a fin structure with a three-dimensional structure. Another feature is that it is highly compatible with 16/14nm logic processes that have the same fin structure. Also, the superlative charge retention characteristics, which are a feature of charge trap type MONOS flash memory, are not degraded even when the fin structure is introduced, and Renesas has verified that the same reliability characteristics as existing devices can be achieved.

The challenge when incorporating this fin structure SG-MONOS flash memory cell in a 16/14nm generation MCU is the increase in sample-to-sample variations associated with increasing the memory capacity. Renesas succeeded in overcoming this issue and verified its operation even in a large-scale memory, which marks a significant advancement towards the achievement of high-performance, high-reliability MCUs that include an embedded flash memory system in the 100 MB class.

In fabricating this prototype, Renesas optimized the process conditions, including the deposition, etching, and ion implantation conditions, for the fin structure and created a memory array without increasing the number of process steps. This will allow the company to increase capacity to the large scales of over 100 MB in a next-generation embedded flash memory it says.

A step pulse write method (ISSP: incremental step pulse programming) in which the write voltage is increased in steps starting at a low voltage was effective in suppressing degradation of device characteristics caused by the enhancement of electric fields at the fin tips. Using this in the array achieves both high-speed write operations and reliability and confirmed almost no influence on write/erase speed even after the 250,000 rewrite cycles that was standard for earlier data storage flash memories.

Data retention under high temperatures is critical for automotive applications. In this prototype, Renesas verified that the device maintains a guaranteed storage time after programming of at least ten years at 160°C, equivalent to earlier devices. Furthermore, this device maintains the sharp threshold voltage distribution that is a characteristic of the fin structure even after data is stored at the high temperature of 160°C at the array level, therefore maintaining the high reliability of existing devices.

Currently, Renesas mass produces MCUs fabricated in a 40nm generation process using SG-MONOS structure flash memory and is also developing 28nm generation MCUs. Based on the demonstration of large-scale memory operation, Renesas plans to develop 16/14nm generation MCUs with a target of 2023 for practical applications and is committed to continuing to contribute to progress in the automotive field and the achievement of a smart society.

www.renesas.com

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