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Monday, October 09, 2017

SiFive adds linux support to RISC-V CPU cores

By Nick Flaherty at

Open source CPU core designers SiFive have launched the first multi-core for embedded designs that uses the RISC-V architecture and supports the linux operating system.

The quad core U54-MC Coreplex IP is based around the MIPS-like RISC-V open source architecture, which is supported by an ecosystem comprising more than 70 companies and has seen significant growth in the embedded segment. Part of this has come from the uncertainty around the future of the MIPS architecture.
The release of the U54-MC Coreplex marks the architecture's expansion into the application processor space and wider IoT applications such as gateways.
The U54-MC contains four U54 CPUs along with a single E51 CPU, and is the first commercial RISC-V core to include multicore support and cache coherence. Each U54 CPU has a highly efficient five-stage in-order pipeline supporting the RV64GC ISA, which is expected to be the standard for Linux-based RISC-V devices.

The 64-bit E51 CPU serves as a management core and is fully coherent with the main U54 cores. This makes it suited to applications which need full operating system support such as AI, machine learning, networking, gateways and smart IoT devices.
"The ability for RISC-V developers to develop Linux and other Unix-based operating systems on commercial grade silicon will enable the RISC-V software ecosystem to quickly expand beyond embedded systems, and bring new solutions to market," said Rick O'Connor, executive director of the non-profit RISC-V Foundation.

The Coreplex has been taped out as part of SiFive's Freedom Unleashed family of high-performance, customisable RISC-V SoCs. This has the U54 and E51 CPUs running at 1.5 GHz in 28nm technology. Each of the U54 CPUs implement a 32KB Instruction Cache and 32KB Data Cache, and all of the cores share a coherent, 2MB L2 Cache. Customers can license the U54-MC Coreplex in a variety of configurations besides the 4+1 default configuration.

"The U54-MC Coreplex is the first fully Linux-compatible CPU based on RISC-V. It takes the industry one step closer to making custom silicon available to everyone," said Andrew Waterman, co-founder of SiFive. "We continue to be amazed by the support SiFive has received since we launched the industry's first open-source RISC-V SoC last year, and look forward to additional milestones in the coming months."

The U54-MC Coreplex can be accessed at A development board based on U54-MC Coreplex IP will be available in Q1 2018. 

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